1. Field of the Invention
The present invention relates to a semiconductor device and in particular to a semiconductor device having a structure suitable for the formation of a vertical channel MOS power transistor.
U.S. Pat. No. 5034785 describes the evolution of double diffused MOS transistors. FIG. 1 of the U.S. patent illustrates an early structure in which in an on-state a field from a gate forms a horizontal conducting chattel, allowing current to flow laterally beneath the gate. After flowing laterally, the current must then flow vertically to reach a drain region. FIG. 2 of the above US patent illustrates an alternative structure generally referred to as a UMOS structure. In that structure, source, body and drain regions are arranged vertically adjacent a trench fondled in a wafer surface, the trench being generally of U-shaped cross-section. Current thus flows more efficiently in the vertical direction only. The structure of FIG. 2 of the above US patent is however difficult to fabricate as it requires the formation of a U-shaped gate lining the sides of the trench and results in a transistor with a non-planar surface. FIG. 3 of the above US patent seeks to provide a UMOS structure which is not subject to these disadvantages by providing a vertical gate in a structure with a planar surface whilst still enabling contact to be made to the gate which is embedded beneath that surface.
2. Description of the Prior Art
In the known structure as illustrated in FIG. 3 of the above US patent, a drain region is overlaid by a body region which defines a substantially planar upper surface. Source regions extend from the upper surface towards the drain region and a series of indentations extend from the upper surface of the body region. The indentations are arranged such that lower side walls of each indentation are defined by portions of the drain and body regions and upper side walls of each indentation are defined by source regions. A lower portion of each indentation is filled with a gate region isolated from the side walls of the indentation by a first insulating layer and covered by a second insulating layer. The indentations are completely filled with the material malting up the gate region and the first and second insulating layers. A source conductor overlies the upper surface of the body region to contact portions of the source regions which are substantially coplanar with the upper surface of the body region. Thus with such an arrangement the resultant device has a flat upper surface.
It is of course desirable to produce power transistors with a relatively low on state resistance for a given lateral area. Accordingly it is desirable to minimise the spacing between adjacent gate and source structures. The known structure described in FIG. 3 of the above US patent does impose certain dimensional limitations however. Firstly, a minimum lateral spacing must be provided between adjacent source regions such that an adequate suppression of carrier injection from the emitter-base junction of the parasitic (source/body/drain) bipolar element is achieved. For each source region, this requires an adequate low resistance path from the overlying source conductor, through the body region, to the point on the boundary of the source region most distant from the overlying source conductor. A further limitation arises in that the lateral width of each source region at the upper surface must be sufficient to provide a contact area between the source region and the source conductor capable of caring the required current Thus the minimum spacing that must be provided between the closest adjacent side walls of two indentations is the sum of the minimum inter-source spacing necessary to provide adequate inhibition of unwanted bipolar conduction and twice the minimum lateral source width for acceptable contact resistance.
It is an object of the present invention to provide a semiconductor structure in which the minimum spacing between adjacent gate regions can be reduced beyond the above-described dimensional limitations
According to the present invention, there is provided a semiconductor device comprising a drain region, a body region overlying the drain region and defining an upper surface, source regions extending from adjacent the upper surface of the body region towards the drain region, and a series of indentations extending into the body region such that lower side walls of each indentation are defined by portions of the drain and body regions and upper side walls of each indentation are defined by the source regions, wherein a lower portion of each indentation is filled with a gate region isolated from the side walls by a first insulating layer and covered by a second insulating layer, a source conductor overlies the upper surface and is electrically connected to the source and body regions, and a gate conductor is electrically connected to each gate region, the source conductor extending into an upper portion of each indentation to contact portions of the upper side walls of the indentation which are defined by the source regions.
The present invention also provides a method for forming a semiconductor as defined in tile preceding paragraph, wherein indentations are formed in a semiconductor wafer, lined with a first insulating layer, and partially filled with a gate material such that lower side walls of each indentation adjacent the gate material are defined by portions of a body region and a drain region and upper side walls of each indentation above the gate material are defined by portions of source regions, a second insulating layer is formed in each indentation to cover the gate region, tile second insulating layer is etched back to a depth such that portions of the upper side walls defined by the source regions are exposed above the second insulating layer, and an electrically conductive layer is deposited on the wafer so as to extend into each indentation and contact the exposed upper side walls defined by the source regions.
Preferably the upper surface of the body region is substantially planar and the source regions define upper surfaces which are substantially coplanar with the upper surface of the body region, the source conductor overlying and electrically contacting the upper surfaces of the source regions.
Given that the source conductor extends into the indentations and contacts surfaces of the source regions which define side walls of the indentations, the total area of contact between the source regions and the source conductor is a function of the width of the portion of each source region which is coplanar with the upper surface of the body region plus the depth of penetration of the source conductor into the upper portion of the indentations. For a given required area of source/source conductor contact. the minimum acceptable dimension of the source regions in the direction separating adjacent gate regions can be reduced as compared with structures in which no source/source conductor contact is made within upper portions of the indentations.
A further advantage which can be realised with the present invention is that the source diffusion distance can be smaller than in prior art devices. This is because in prior art devices the source is contacted by the source conductor only on the upper surface of the device, the area of contact being proportional to the diffusion distance assuming that the source is formed by diffusion from the indentation walls. In contrast, with the present invention, the source is contacted by the source conductor within the indentation and it is not therefore necessary to have a relatively large source diffusion distance to achieve an adequate lateral contact width. Given that relatively small source diffusion distances can be used, very accurate channel width definition is possible using very accurate techniques such as rapid thermal annealing Manufacturing tolerances with regard to the channel width, necessary to accommodate variations in source diffusion distance, can be very much reduced.